LM3S5G31 Datasheet, PDF (30/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Table of Contents
Register 58: USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............... 939
Register 59: USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8), offset 0x182 ............... 939
Register 60: USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9), offset 0x192 ............... 939
Register 61: USB Transmit Control and Status Endpoint 10 Low (USBTXCSRL10), offset 0x1A2 ........... 939
Register 62: USB Transmit Control and Status Endpoint 11 Low (USBTXCSRL11), offset 0x1B2 ........... 939
Register 63: USB Transmit Control and Status Endpoint 12 Low (USBTXCSRL12), offset 0x1C2 .......... 939
Register 64: USB Transmit Control and Status Endpoint 13 Low (USBTXCSRL13), offset 0x1D2 .......... 939
Register 65: USB Transmit Control and Status Endpoint 14 Low (USBTXCSRL14), offset 0x1E2 ........... 939
Register 66: USB Transmit Control and Status Endpoint 15 Low (USBTXCSRL15), offset 0x1F2 ........... 939
Register 67: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 .............. 942
Register 68: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ............. 942
Register 69: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ............. 942
Register 70: USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ............. 942
Register 71: USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ............. 942
Register 72: USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ............. 942
Register 73: USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ............. 942
Register 74: USB Transmit Control and Status Endpoint 8 High (USBTXCSRH8), offset 0x183 ............. 942
Register 75: USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 ............. 942
Register 76: USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 ......... 942
Register 77: USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 .......... 942
Register 78: USB Transmit Control and Status Endpoint 12 High (USBTXCSRH12), offset 0x1C3 ......... 942
Register 79: USB Transmit Control and Status Endpoint 13 High (USBTXCSRH13), offset 0x1D3 ......... 942
Register 80: USB Transmit Control and Status Endpoint 14 High (USBTXCSRH14), offset 0x1E3 ......... 942
Register 81: USB Transmit Control and Status Endpoint 15 High (USBTXCSRH15), offset 0x1F3 ......... 942
Register 82: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ........................... 945
Register 83: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ........................... 945
Register 84: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ........................... 945
Register 85: USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ........................... 945
Register 86: USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ........................... 945
Register 87: USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ........................... 945
Register 88: USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ........................... 945
Register 89: USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset 0x184 ........................... 945
Register 90: USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset 0x194 ........................... 945
Register 91: USB Maximum Receive Data Endpoint 10 (USBRXMAXP10), offset 0x1A4 ....................... 945
Register 92: USB Maximum Receive Data Endpoint 11 (USBRXMAXP11), offset 0x1B4 ....................... 945
Register 93: USB Maximum Receive Data Endpoint 12 (USBRXMAXP12), offset 0x1C4 ...................... 945
Register 94: USB Maximum Receive Data Endpoint 13 (USBRXMAXP13), offset 0x1D4 ...................... 945
Register 95: USB Maximum Receive Data Endpoint 14 (USBRXMAXP14), offset 0x1E4 ....................... 945
Register 96: USB Maximum Receive Data Endpoint 15 (USBRXMAXP15), offset 0x1F4 ....................... 945
Register 97: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............... 947
Register 98: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............... 947
Register 99: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............... 947
Register 100: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............... 947
Register 101: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............... 947
Register 102: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............... 947
Register 103: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............... 947
Register 104: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ............... 947
Register 105: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ............... 947
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July 03, 2014
Texas Instruments-Production Data