LM3S5G31 Datasheet, PDF (24/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Table of Contents
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
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Register 17:
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Register 31:
Register 32:
EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ................................... 529
EPI Address Map (EPIADDRMAP), offset 0x01C ............................................................. 530
EPI Read Size 0 (EPIRSIZE0), offset 0x020 .................................................................... 532
EPI Read Size 1 (EPIRSIZE1), offset 0x030 .................................................................... 532
EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ 533
EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ 533
EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 534
EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 534
EPI Status (EPISTAT), offset 0x060 ................................................................................ 536
EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 538
EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................ 539
EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 539
EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 539
EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 539
EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 539
EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 539
EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 539
EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 539
EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 540
EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 542
EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 543
EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 544
EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 546
EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C .................................... 547
General-Purpose Timers ............................................................................................................. 549
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 566
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 567
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 569
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 571
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 574
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 576
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 579
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 582
Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 584
Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 585
Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 586
Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 587
Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 588
Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 589
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 590
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 591
Register 17: GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 592
Register 18: GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 593
Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 594
Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 595
Watchdog Timers ......................................................................................................................... 596
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 600
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 601
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July 03, 2014
Texas Instruments-Production Data