LM3S5G31 Datasheet, PDF (26/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Table of Contents
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ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 685
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 685
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 686
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 686
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 688
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 689
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 690
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 691
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 692
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 697
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 697
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 697
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 697
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 697
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 697
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 697
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 697
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 700
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 700
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 700
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 700
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 700
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 700
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 700
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 700
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 702
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 717
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 719
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 722
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 725
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 726
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 727
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 728
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 730
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 734
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 736
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 740
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 744
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 748
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 750
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 751
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 752
Register 17: UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 753
Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 754
Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 755
Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 756
Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 757
Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 758
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July 03, 2014
Texas Instruments-Production Data