LM3S5G31 Datasheet, PDF (23/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Register 28:
Register 29:
Register 30:
Register 31:
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 415
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 416
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 417
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 418
General-Purpose Input/Outputs (GPIOs) ................................................................................... 419
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 432
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 433
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 434
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 435
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 436
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 437
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 438
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 439
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 441
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 442
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 444
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 445
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 446
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 447
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 448
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 450
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 452
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 453
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 455
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 456
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 458
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 460
Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 462
Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 463
Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 464
Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 465
Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 466
Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 467
Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 468
Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 469
Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 470
Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 471
Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 472
Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 473
External Peripheral Interface (EPI) ............................................................................................. 474
Register 1: EPI Configuration (EPICFG), offset 0x000 ....................................................................... 506
Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 ................................................................. 507
Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 .............................................. 509
Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ............................................... 511
Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ........................................... 514
Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................ 518
Register 7: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 .......................................... 523
Register 8: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 526
July 03, 2014
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