LM3S5G31 Datasheet, PDF (185/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
5.2.1
5.2.2
5.2.2.1
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 198
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, Flash memory size, and other features. See the DID0 (page 203), DID1
(page 231), DC0-DC9 (page 233) and NVMSTAT (page 255) registers.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
Reset Sources
The LM3S5G31 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 186).
2. External reset input pin (RST) assertion (see page 186).
3. Internal brown-out (BOR) detector (see page 188).
4. Software-initiated reset (with the software reset registers) (see page 188).
5. A watchdog timer reset condition violation (see page 189).
6. MOSC failure (see page 190).
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
Reset Source
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Yes
Yes
Yes
RST
Yes
Yes
Yes
Brown-Out Reset
Yes
Yes
Yes
Software System Request
Yes
Yes
Yes
Reset using the SYSRESREQ
bit in the APINT register.
Software System Request
Yes
No
No
Reset using the VECTRESET
bit in the APINT register.
Software Peripheral Reset
No
Yes
Yes^a
Watchdog Reset
Yes
Yes
Yes
MOSC Failure Reset
Yes
Yes
Yes
a. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
or an external reset is the cause, and then all the other bits in the RESC register are cleared except
for the POR or EXT indicator.
July 03, 2014
185
Texas Instruments-Production Data