LM3S5G31 Datasheet, PDF (13/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 773
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 774
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 774
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 775
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 776
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 777
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 777
Figure 16-1. I²C Block Diagram ............................................................................................. 809
Figure 16-2. I²C Bus Configuration ........................................................................................ 810
Figure 16-3. START and STOP Conditions ............................................................................. 811
Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 811
Figure 16-5. R/S Bit in First Byte ............................................................................................ 812
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 812
Figure 16-7. Master Single TRANSMIT .................................................................................. 816
Figure 16-8. Master Single RECEIVE ..................................................................................... 817
Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 818
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 819
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 820
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 821
Figure 16-13. Slave Command Sequence ................................................................................ 822
Figure 17-1. CAN Controller Block Diagram ............................................................................ 847
Figure 17-2. CAN Data/Remote Frame .................................................................................. 849
Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 857
Figure 17-4. CAN Bit Time .................................................................................................... 861
Figure 18-1. USB Module Block Diagram ............................................................................... 896
Figure 19-1. Analog Comparator Module Block Diagram ......................................................... 964
Figure 19-2. Structure of Comparator Unit .............................................................................. 966
Figure 19-3. Comparator Internal Reference Structure ............................................................ 967
Figure 20-1. PWM Module Diagram ....................................................................................... 979
Figure 20-2. PWM Generator Block Diagram .......................................................................... 979
Figure 20-3. PWM Count-Down Mode .................................................................................... 983
Figure 20-4. PWM Count-Up/Down Mode .............................................................................. 984
Figure 20-5. PWM Generation Example In Count-Up/Down Mode ........................................... 984
Figure 20-6. PWM Dead-Band Generator ............................................................................... 985
Figure 21-1. QEI Block Diagram .......................................................................................... 1052
Figure 21-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1055
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1074
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1075
Figure 25-1. Load Conditions ............................................................................................... 1146
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1147
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1147
Figure 25-4. Power-On Reset Timing ................................................................................... 1148
Figure 25-5. Brown-Out Reset Timing .................................................................................. 1148
Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1149
Figure 25-7. External Reset Timing (RST) ............................................................................ 1149
Figure 25-8. Software Reset Timing ..................................................................................... 1149
July 03, 2014
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Texas Instruments-Production Data