LM3S5G31 Datasheet, PDF (382/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Micro Direct Memory Access (μDMA)
Table 8-13. μDMA Register Map (continued)
Offset Name
Type
Reset
Description
0xFFC DMAPCellID3
RO
0x0000.00B1 DMA PrimeCell Identification 3
See
page
418
8.5 μDMA Channel Control Structure
The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel
has two control structures, which are located in a table in system memory. Refer to “Channel
Configuration” on page 363 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary
and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and
so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
382
July 03, 2014
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