LM3S5G31 Datasheet, PDF (525/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Bit/Field
20
19:8
7:6
5:4
3:0
Name
RDHIGH
reserved
WRWS
RDWS
reserved
Type
R/W
Reset
0
Description
CS1n READ Strobe Polarity
This field is used if the CSBAUD bit in the EPIHBnCFG2 register is
enabled.
Value Description
0 The READ strobe for CS1n accesses is RDn (active Low).
1 The READ strobe for CS1n accesses is RD (active High).
RO
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0x0
CS1n Write Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state encoding adds 2 EPI clock cycles to the access time.
Value Description
0x0 Active WRn is 2 EPI clocks.
0x1 Active WRn is 4 EPI clocks
0x2 Active WRn is 6 EPI clocks
0x3 Active WRn is 8 EPI clocks
R/W
0x0
CS1n Read Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state encoding adds 2 EPI clock cycles to the access
time.
Value Description
0x0 Active RDn is 2 EPI clocks
0x1 Active RDn is 4 EPI clocks
0x2 Active RDn is 6 EPI clocks
0x3 Active RDn is 8 EPI clocks
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 03, 2014
525
Texas Instruments-Production Data