LM3S5G31 Datasheet, PDF (3/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 34
About This Document .................................................................................................................... 38
Audience .............................................................................................................................................. 38
About This Manual ................................................................................................................................ 38
Related Documents ............................................................................................................................... 38
Documentation Conventions .................................................................................................................. 39
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
1.4
Architectural Overview .......................................................................................... 41
Overview ...................................................................................................................... 41
Target Applications ........................................................................................................ 43
Features ....................................................................................................................... 43
ARM Cortex-M3 Processor Core .................................................................................... 43
On-Chip Memory ........................................................................................................... 45
External Peripheral Interface ......................................................................................... 46
Serial Communications Peripherals ................................................................................ 48
System Integration ........................................................................................................ 52
Advanced Motion Control ............................................................................................... 57
Analog .......................................................................................................................... 59
JTAG and ARM Serial Wire Debug ................................................................................ 61
Packaging and Temperature .......................................................................................... 62
Hardware Details .......................................................................................................... 62
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
The Cortex-M3 Processor ...................................................................................... 63
Block Diagram .............................................................................................................. 64
Overview ...................................................................................................................... 65
System-Level Interface .................................................................................................. 65
Integrated Configurable Debug ...................................................................................... 65
Trace Port Interface Unit (TPIU) ..................................................................................... 66
Cortex-M3 System Component Details ........................................................................... 66
Programming Model ...................................................................................................... 67
Processor Mode and Privilege Levels for Software Execution ........................................... 67
Stacks .......................................................................................................................... 67
Register Map ................................................................................................................ 68
Register Descriptions .................................................................................................... 69
Exceptions and Interrupts .............................................................................................. 82
Data Types ................................................................................................................... 82
Memory Model .............................................................................................................. 82
Memory Regions, Types and Attributes ........................................................................... 84
Memory System Ordering of Memory Accesses .............................................................. 85
Behavior of Memory Accesses ....................................................................................... 85
Software Ordering of Memory Accesses ......................................................................... 85
Bit-Banding ................................................................................................................... 87
Data Storage ................................................................................................................ 89
Synchronization Primitives ............................................................................................. 90
Exception Model ........................................................................................................... 91
Exception States ........................................................................................................... 92
Exception Types ............................................................................................................ 92
July 03, 2014
3
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