LM3S5G31 Datasheet, PDF (685/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070
Register 31: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090
This register determines whether the sample from the given conversion on Sample Sequence n is
saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1
register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADC Sample Sequence 1 Operation (ADCSSOP1)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x070
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
S3DCOP
reserved
S2DCOP
reserved
S1DCOP
reserved
S0DCOP
Type RO
RO
RO
R/W
RO
RO
RO
R/W
RO
RO
RO
R/W
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:13
12
Name
reserved
S3DCOP
Type
RO
R/W
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Sample 3 Digital Comparator Operation
Value Description
1 The fourth sample is sent to the digital comparator unit specified
by the S3DCSEL bit in the ADCSSDC0n register, and the value
is not written to the FIFO.
0 The fourth sample is saved in Sample Sequence FIFOn.
11:9
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
S2DCOP
R/W
0
Sample 2 Digital Comparator Operation
Same definition as S3DCOP but used during the third sample.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
S1DCOP
R/W
0
Sample 1 Digital Comparator Operation
Same definition as S3DCOP but used during the second sample.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
S0DCOP
R/W
0
Sample 0 Digital Comparator Operation
Same definition as S3DCOP but used during the first sample.
July 03, 2014
685
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