LM3S5G31 Datasheet, PDF (312/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Hibernation Module
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store state information and does not lose power during a power cut
operation as long as a battery is present.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 288.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTD
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTD
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
RTD
Type
R/W
Reset
-
Description
Hibernation Module NV Data
312
July 03, 2014
Texas Instruments-Production Data