LM3S5G31 Datasheet, PDF (1022/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Pulse Width Modulator (PWM)
Register 18: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 19: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 20: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred.
Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register.
PWM0 Raw Interrupt Status (PWM0RIS)
PWM0 base: 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
4
Name
reserved
INTCMPBD
INTCMPBU
Type
RO
RO
RO
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator B Down Interrupt Status
Value Description
1 The counter has matched the value in the PWMnCMPB register
while counting down.
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC
register.
Comparator B Up Interrupt Status
Value Description
1 The counter has matched the value in the PWMnCMPB register
while counting up.
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC
register.
1022
Texas Instruments-Production Data
July 03, 2014