LM3S5G31 Datasheet, PDF (855/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a
Transmit Message Object” on page 851 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
5. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
■ Clear the RMTEN bit to leave the TXRQST bit unchanged
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
17.3.11
Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
July 03, 2014
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