LM3S5G31 Datasheet, PDF (546/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

External Peripheral Interface (EPI)
Register 31: EPI Masked Interrupt Status (EPIMIS), offset 0x218
This register is the masked interrupt status register. On read, it gives the current state of each
interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no
effect.
The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register,
the interrupt is sent to the interrupt controller.
EPI Masked Interrupt Status (EPIMIS)
Base 0x400D.0000
Offset 0x218
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WRMIS RDMIS ERRMIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
Name
reserved
WRMIS
Type
RO
RO
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write Masked Interrupt Status
Value Description
0 The number of available entries in the WFIFO is above the range
specified by the trigger level or the interrupt is masked.
1 The number of available entries in the WFIFO is within the range
specified by the trigger level (the WRFIFO field in the
EPIFIFOLVL register) and the WRIM bit in the EPIIM register is
set, triggering an interrupt to the interrupt controller.
1
RDMIS
RO
0
Read Masked Interrupt Status
Value Description
0 The number of valid entries in the NBRFIFO is below the range
specified by the trigger level or the interrupt is masked.
1 The number of valid entries in the NBRFIFO is within the range
specified by the trigger level (the RDFIFO field in the
EPIFIFOLVL register) and the RDIM bit in the EPIIM register is
set, triggering an interrupt to the interrupt controller.
0
ERRMIS
RO
0
Error Masked Interrupt Status
Value Description
0 An error has not occurred or the interrupt is masked.
1 A WFIFO Full, a Read Stalled, or a Timeout error has occurred
and the ERIM bit in the EPIIM register is set, triggering an
interrupt to the interrupt controller.
546
July 03, 2014
Texas Instruments-Production Data