LM3S5G31 Datasheet, PDF (400/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Micro Direct Memory Access (μDMA)
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset
0x024
Each bit of the DMAREQMASKCLR register represents the corresponding μDMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register.
DMA Channel Request Mask Clear (DMAREQMASKCLR)
Base 0x400F.F000
Offset 0x024
Type WO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
CLR[n]
Type
WO
Reset
-
Description
Channel [n] Request Mask Clear
Value Description
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the
DMAREQMASKSET register meaning that the peripheral
associated with channel [n] is enabled to request μDMA
transfers.
400
July 03, 2014
Texas Instruments-Production Data