LM3S5G31 Datasheet, PDF (720/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
2
1
0
Name
BE
PE
FE
Type
RO
RO
RO
Reset
0
0
0
Description
UART Break Error
Value Description
1 A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
0 No break condition has occurred
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
UART Parity Error
Value Description
1 The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
0 No parity error has occurred
This bit is cleared to 0 by a write to UARTECR.
UART Framing Error
Value Description
1 The received character does not have a valid stop bit (a valid
stop bit is 1).
0 No framing error has occurred
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Write-Only Error Clear Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DATA
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
720
July 03, 2014
Texas Instruments-Production Data