LM3S5G31 Datasheet, PDF (380/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Micro Direct Memory Access (μDMA)
8.3.4.5
8.3.5
8.4
Process Interrupts
The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary
channel control structure. When the primary transfer to buffer A is complete, it switches to the
alternate channel control structure and makes transfers into buffer B. At the same time, the primary
channel control word mode field is configured to indicate Stopped, and an interrupt is
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data or set a flag that the data must be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
a. Process the newly received data in buffer A or signal the buffer processing code that buffer
A has data available.
b. Reprogram the primary channel control word at offset 0x88 according to Table
8-12 on page 379.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
8-12 on page 379.
Configuring Channel Assignments
Channel assignments for each μDMA channel can be changed using the DMACHASGN register.
Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the
channel.
Refer to Table 8-1 on page 361 for channel assignments.
For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of the DMACHASGN
register.
Register Map
Table 8-13 on page 381 lists the μDMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in system memory, and the location is determined by the application, that is, the base
address is n/a (not applicable). In the table below, the offset for the channel control structures is the
offset from the entry in the channel control table. See “Channel Configuration” on page 363 and Table
8-3 on page 364 for a description of how the entries in the channel control table are located in memory.
The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base
address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers
can be programmed (see page 273). There must be a delay of 3 system clocks after the μDMA
module clock is enabled before any μDMA module registers are accessed.
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July 03, 2014
Texas Instruments-Production Data