LM3S5G31 Datasheet, PDF (12/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Table of Contents
Figure 10-11. Write Followed by Read to External FIFO ............................................................ 496
Figure 10-12. Two-Entry FIFO ................................................................................................. 496
Figure 10-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 500
Figure 10-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 500
Figure 10-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 501
Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 501
Figure 10-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 501
Figure 10-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 502
Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 502
Figure 10-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 502
Figure 10-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 502
Figure 10-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 503
Figure 10-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 504
Figure 10-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 504
Figure 11-1. GPTM Module Block Diagram ............................................................................ 550
Figure 11-2. Timer Daisy Chain ............................................................................................. 555
Figure 11-3. Input Edge-Count Mode Example ....................................................................... 557
Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 559
Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 560
Figure 12-1. WDT Module Block Diagram .............................................................................. 597
Figure 13-1. Implementation of Two ADC Blocks .................................................................... 622
Figure 13-2. ADC Module Block Diagram ............................................................................... 623
Figure 13-3. ADC Sample Phases ......................................................................................... 627
Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 628
Figure 13-5. Skewed Sampling .............................................................................................. 628
Figure 13-6. Sample Averaging Example ............................................................................... 629
Figure 13-7. ADC Input Equivalency Diagram ......................................................................... 630
Figure 13-8. Internal Voltage Conversion Result ..................................................................... 631
Figure 13-9. External Voltage Conversion Result with 3.0-V Setting ......................................... 632
Figure 13-10. External Voltage Conversion Result with 1.0-V Setting ......................................... 632
Figure 13-11. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 634
Figure 13-12. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 634
Figure 13-13. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 635
Figure 13-14. Internal Temperature Sensor Characteristic ......................................................... 636
Figure 13-15. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 638
Figure 13-16. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 639
Figure 13-17. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 640
Figure 14-1. UART Module Block Diagram ............................................................................. 703
Figure 14-2. UART Character Frame ..................................................................................... 706
Figure 14-3. IrDA Data Modulation ......................................................................................... 708
Figure 14-4. LIN Message ..................................................................................................... 710
Figure 14-5. LIN Synchronization Field ................................................................................... 711
Figure 15-1. SSI Module Block Diagram ................................................................................. 767
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 771
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 771
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 772
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 772
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July 03, 2014
Texas Instruments-Production Data