LM3S5G31 Datasheet, PDF (1178/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE4, type R/W, offset 0x210, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE5, type R/W, offset 0x214, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE6, type R/W, offset 0x218, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE7, type R/W, offset 0x21C, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE4, type R/W, offset 0x410, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE5, type R/W, offset 0x414, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE6, type R/W, offset 0x418, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE7, type R/W, offset 0x41C, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
Micro Direct Memory Access (μDMA)
μDMA Channel Control Structure (Offset from Channel Control Table Base)
Base n/a
DMASRCENDP, type R/W, offset 0x000, reset -
ADDR
ADDR
DMADSTENDP, type R/W, offset 0x004, reset -
ADDR
ADDR
DMACHCTL, type R/W, offset 0x008, reset -
DSTINC
DSTSIZE
SRCINC
SRCSIZE
ARBSIZE
ARBSIZE
XFERSIZE
XFERMODE
1178
Texas Instruments-Production Data
July 03, 2014