LM3S5G31 Datasheet, PDF (25/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
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Register 20:
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 602
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 604
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 605
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 606
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 607
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 608
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 609
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 610
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 611
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 612
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 613
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 614
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 615
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 616
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 617
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 618
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 619
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 620
Analog-to-Digital Converter (ADC) ............................................................................................. 621
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 644
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 645
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 647
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 649
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 652
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 654
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 659
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 660
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 662
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 664
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 666
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 667
Register 13: ADC Control (ADCCTL), offset 0x038 ............................................................................. 669
Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 670
Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 672
Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 675
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 675
Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 675
Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 675
Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 676
Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 676
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 676
Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 676
Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 678
Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 680
Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 682
Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 682
Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 683
Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 683
July 03, 2014
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