LM3S5G31 Datasheet, PDF (22/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Table of Contents
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
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Register 30:
Register 31:
Register 32:
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 338
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 339
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 341
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 342
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 343
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 344
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 345
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 346
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 347
Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 .................................... 348
Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 .................................... 349
Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218 .................................... 350
Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ................................... 351
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 352
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 353
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 354
Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 355
Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 356
Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 357
Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 358
Micro Direct Memory Access (μDMA) ........................................................................................ 359
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 383
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 384
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 385
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 390
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 392
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 393
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 394
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 395
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 396
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 397
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 398
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 399
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 400
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 401
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 402
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 403
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 404
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 405
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 406
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 407
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 408
Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 409
Register 23: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 410
Register 24: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 411
Register 25: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 412
Register 26: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 413
Register 27: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 414
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July 03, 2014
Texas Instruments-Production Data