LM3S5G31 Datasheet, PDF (34/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S5G31
data sheet.
Table 1. Revision History
Date
July 2014
Revision Description
15852.2743 ■ In JTAG chapter, clarified JTAG-to-SWD Switching and SWD-to-JTAG Switching.
■ In System Control chapter, clarified behavior of Reset Cause (RESC) register external reset bit.
■ In Internal memory chapter, noted that the Boot Configuration (BOOTCFG) register requires a
POR before committed changes to the Flash-resident registers take effect.
■ In GPIO chapter, corrected values for GPIOPCTL in the table GPIO Pins With Non-Zero Reset
Values.
■ In UART chapter, clarified that the transmit interrupt is based on a transition through level.
■ In Ordering and Contact Information appendix, moved orderable part numbers table to addendum.
■ Additional minor data sheet clarifications and corrections.
October 2012
13440.2549 ■ Marked LM3S5G31 device as not recommended for new designs (NRND). Device is in production
to support existing customers, but TI does not recommend using this part in a new design.
■ In the uDMA chapter, in the "μDMA Channel Assignments" and "Request Type Support" tables,
corrected to show uDMA support for burst requests from the general-purpose timer, not single
requests.
■ In the Watchdog Timers chapter, added information on servicing the watchdog timer to the
Initialization and Configuration section.
■ In the General-Purpose Timers chapter, added note to the GPTMTnV registers that in 16-bit mode,
only the lower 16-bits of the register can be written with a new value. Writes to the prescaler bits
have no effect.
■ Corrected reset for the UART Raw Interrupt Status (UARTRIS) register.
■ In the USB chapter, removed reference to USB low-speed operation including deleting the USB
Low-Speed Last Transaction to End of Frame Timing (USBLSEOF) register and the FORCEFS
bit in the USB Test Mode (USBTEST) register. Low-speed operation is not valid in USB device-only
mode.
■ In the USB chapter, clarified that the USB PHY has internal termination resistors, and thus there is
no need for external resistors.
■ In the Electrical Characteristics chapter, added clarifying footnote to the GPIO Module Characteristics
table.
■ Additional minor data sheet clarifications and corrections.
January 2012
11425
■ In System Control chapter:
– Clarified that an external LDO cannot be used.
– Clarified system clock requirements when the ADC module is in operation.
– Added important note to write the RCC register before the RCC2 register.
■ In Hibernation chapter:
– Changed terminology from non-volatile memory to battery-backed memory.
34
July 03, 2014
Texas Instruments-Production Data