LM3S5G31 Datasheet, PDF (486/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

External Peripheral Interface (EPI)
external latch to capture the address then hold it until the data phase. CSn is best used for Host-Bus
unmuxed mode in which EPI address and data pins are separate. The CSn indicates when the
address and data phases of a read or write access are occurring. Both the ALE and the CSn modes
can be enhanced to access external devices using settings in the EPIHBnCFG2 register. Wait states
can be added to the data phase of the access using the WRWS and RDWS bits in the EPIHBnCFG2
register.
For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and
output to what the XFIFO can handle.
Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect
external devices to the EPI signals, as well as control whether byte select signals are provided in
HB16 mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG
register and the CSCFG fieldin the EPIHBnCFG2 register, and the BSEL bit in the EPIHB16CFG
register. The CSCFGEXT bit extends the chip select configuration possibilities by providing the most
significant bit of the CSCFG field.
If one of the Dual-Chip-Select modes is selected (CSCFG is 0x2 or 0x3 in the EPIHBnCFG2 register),
both chip selects can share the peripheral or the memory space, or one chip select can use the
peripheral space and the other can use the memory space. In the EPIADDRMAP register, if the
EPADR field is not 0x0 and the ERADR field is 0x0, then the address specified by EPADR is used for
both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n
being asserted when the MSB of the address range is 1. If the ERADR field is not 0x0 and the EPADR
field is 0x0, then the address specified by ERADR is used for both chip selects, with the MSB
performing the same delineation. If both the EPADR and the ERADR are not 0x0, then CS0n is asserted
for either address range defined by EPADR and CS1n is asserted for either address range defined
by ERADR.
If the CSBAUD bit in the EPIHBnCFG2 register is set in Dual-chip select mode, the 2 chip selects
can use different clock frequencies, wait states and strobe polarity. If the CSBAUD bit is clear, both
chip selects use the clock frequency, wait states, and strobe polarity defined for CS0n.
When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data
can be read and written at any address, however these signals reduce the available address width
by 2 pins. The byte select signals are active Low. BSEL0n corresponds to the LSB of the halfword,
and BSEL1n corresponds to the MSB of the halfword.
When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes
at even addresses write invalid values into the odd byte. As a result, accesses should be made as
half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long
int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte
boundaries, the available address space is doubled. For example, 28 bits of address accesses 512
MB in this mode. Table 10-4 on page 486 shows the capabilities of the HB8 and HB16 modes as
well as the available address bits with the possible combinations of these bits.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system.
Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes
Host Bus Type MODE
HB8
0x0
HB8
0x0
HB8
0x0
CSCFG
0x0, 0x1
0x2
0x3
Max # of
External
Devices
1
2
2
BSEL
N/A
N/A
N/A
Byte Access
Always
Always
Always
Available
Address
28 bits
27 bits
26 bits
Addressable
Memory
256 MB
128 MB
64 MB
486
July 03, 2014
Texas Instruments-Production Data