LM3S5G31 Datasheet, PDF (298/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Hibernation Module
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 288.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCM0
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCM0
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit/Field
31:0
Name
RTCM0
Type
Reset Description
R/W 0xFFFF.FFFF RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
298
July 03, 2014
Texas Instruments-Production Data