LM3S5G31 Datasheet, PDF (21/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
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Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 233
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 234
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 236
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 238
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 241
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 243
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 245
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 246
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 250
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 253
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 255
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 256
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 259
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 262
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 264
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 267
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 270
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 273
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 275
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 277
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 279
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 281
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 284
Hibernation Module ..................................................................................................................... 286
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 297
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 298
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 299
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 300
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 301
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 304
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 306
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 308
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 310
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 311
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 312
Internal Memory ........................................................................................................................... 313
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 324
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 325
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 326
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 329
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 330
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 331
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 332
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 333
Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 334
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 335
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 336
Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 337
July 03, 2014
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