LM3S5G31 Datasheet, PDF (429/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Table 9-4. GPIO Pad Configuration Examples (continued)
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
Digital Input/Output
1
X
0
(UART)
Analog Input
(Comparator)
0
0
0
Digital Output
(Comparator)
1
X
0
a. X=Ignored (don’t care bit)
DEN
1
0
1
PUR
?
0
?
?=Can be either 0 or 1, depending on the configuration
PDR
?
0
?
DR2R
?
X
?
DR4R
?
X
?
DR8R
?
X
?
SLR
?
X
?
Table 9-5. GPIO Interrupt Configuration Example
Register
Desired Interrupt
Event Trigger
Pin 2 Bit Value^a
7
6
GPIOIS
0=edge
1=level
X
X
GPIOIBE
0=single edge
X
X
1=both edges
GPIOIEV
0=Low level, or falling X
X
edge
1=High level, or rising
edge
GPIOIM
0=masked
0
0
1=not masked
a. X=Ignored (don’t care bit)
5
X
X
X
0
4
X
X
X
0
3
X
X
X
0
2
0
0
1
1
1
X
X
X
0
0
X
X
X
0
9.4 Register Map
Table 9-7 on page 430 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers
the same register map but provides better back-to-back access performance than the APB bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data.
The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s
base address:
■ GPIO Port A (APB): 0x4000.4000
■ GPIO Port A (AHB): 0x4005.8000
■ GPIO Port B (APB): 0x4000.5000
■ GPIO Port B (AHB): 0x4005.9000
■ GPIO Port C (APB): 0x4000.6000
■ GPIO Port C (AHB): 0x4005.A000
■ GPIO Port D (APB): 0x4000.7000
■ GPIO Port D (AHB): 0x4005.B000
July 03, 2014
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Texas Instruments-Production Data