LM3S5G31 Datasheet, PDF (120/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Cortex-M3 Peripherals
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
31
30
29
28
27
26
25
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
Type R/WC
Reset
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
R/WC
0
24
23
RO
R/WC
0
0
8
7
CURRENT
R/WC
0
R/WC
0
22
R/WC
0
6
R/WC
0
21
R/WC
0
5
R/WC
0
20
19
CURRENT
R/WC
0
R/WC
0
4
3
R/WC
0
R/WC
0
18
R/WC
0
2
R/WC
0
17
R/WC
0
1
R/WC
0
16
R/WC
0
0
R/WC
0
Bit/Field
31:24
23:0
Name
reserved
CURRENT
Type
RO
R/WC
Reset Description
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00.0000
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
3.4 NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 140.
120
July 03, 2014
Texas Instruments-Production Data