LM3S5G31 Datasheet, PDF (5/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
5.5 Register Descriptions .................................................................................................. 202
6
Hibernation Module .............................................................................................. 286
6.1 Block Diagram ............................................................................................................ 287
6.2 Signal Description ....................................................................................................... 287
6.3 Functional Description ................................................................................................. 288
6.3.1 Register Access Timing ............................................................................................... 288
6.3.2 Hibernation Clock Source ............................................................................................ 289
6.3.3 System Implementation ............................................................................................... 290
6.3.4 Battery Management ................................................................................................... 291
6.3.5 Real-Time Clock .......................................................................................................... 291
6.3.6 Battery-Backed Memory .............................................................................................. 292
6.3.7 Power Control Using HIB ............................................................................................. 292
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 292
6.3.9 Initiating Hibernate ...................................................................................................... 292
6.3.10 Waking from Hibernate ................................................................................................ 292
6.3.11 Interrupts and Status ................................................................................................... 293
6.4 Initialization and Configuration ..................................................................................... 293
6.4.1 Initialization ................................................................................................................. 293
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 294
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 294
6.4.4 External Wake-Up from Hibernation .............................................................................. 295
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 295
6.5 Register Map .............................................................................................................. 295
6.6 Register Descriptions .................................................................................................. 296
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 313
Block Diagram ............................................................................................................ 313
Functional Description ................................................................................................. 313
SRAM ........................................................................................................................ 314
ROM .......................................................................................................................... 314
Flash Memory ............................................................................................................. 316
Register Map .............................................................................................................. 321
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 323
Memory Register Descriptions (System Control Offset) .................................................. 335
8
Micro Direct Memory Access (μDMA) ................................................................ 359
8.1 Block Diagram ............................................................................................................ 360
8.2 Functional Description ................................................................................................. 360
8.2.1 Channel Assignments .................................................................................................. 361
8.2.2 Priority ........................................................................................................................ 362
8.2.3 Arbitration Size ............................................................................................................ 362
8.2.4 Request Types ............................................................................................................ 363
8.2.5 Channel Configuration ................................................................................................. 363
8.2.6 Transfer Modes ........................................................................................................... 365
8.2.7 Transfer Size and Increment ........................................................................................ 373
8.2.8 Peripheral Interface ..................................................................................................... 373
8.2.9 Software Request ........................................................................................................ 373
8.2.10 Interrupts and Errors .................................................................................................... 374
8.3 Initialization and Configuration ..................................................................................... 374
8.3.1 Module Initialization ..................................................................................................... 374
July 03, 2014
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