LM3S5G31 Datasheet, PDF (495/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual CSn
ALE
(EPI0S30)
CS0n/CS1n
(EPI0S26/EPI0S27)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
(high order, non muxed)
Muxed
Address/Data
Address
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
Figure 10-10 on page 495 shows continuous read mode accesses. In this mode, reads are performed
by keeping the read mode selected (output enable is asserted) and then changing the address pins.
The data pins are changed by the SRAM after the address pins change.
Figure 10-10. Continuous Read Mode Accesses
OEn
Address
Addr1
Addr2
Addr3
Data
Data1
Data2
Data3
FIFO mode accesses are the same as normal read and write accesses, except that the ALE signal
and address pins are not present. Two input signals can be used to indicate when the XFIFO is full
or empty to gate transactions and avoid overruns and underruns. The FFULL and FEMPTY signals
are synchronized and must be recognized as asserted by the microcontroller for 2 system clocks
before they affect transaction status. The MAXWAIT field in the EPIHBnCFG register defines the
maximum number of EPI clocks to wait while the FEMPTY or FFULL signal is holding off a transaction.
Figure 10-11 on page 496 shows how the FEMPTY signal should respond to a write and read from
the XFIFO. Figure 10-12 on page 496 shows how the FEMPTY and FFULL signals should respond
to 2 writes and 1 read from an external FIFO that contains two entries.
July 03, 2014
495
Texas Instruments-Production Data