LM3S5G31 Datasheet, PDF (949/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
Bit/Field
2
1
0
Name
OVER
FULL
RXRDY
Type
R/W
RO
R/W
Reset
0
0
Description
Overrun
Value Description
0 No overrun error.
1 Indicates that an OUT packet cannot be loaded into the receive
FIFO.
Software must clear this bit.
Note: This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
FIFO Full
Value Description
0 The receive FIFO is not full.
1 No more packets can be loaded into the receive FIFO.
0
Receive Packet Ready
Value Description
0 No data packet has been received.
1 A data packet has been received. The EPn bit in the USBRXIS
register is also set in this situation.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit
is automatically cleared when a packet of USBRXMAXPn bytes has
been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if
packets of less than the maximum packet size are unloaded, then
software must clear this bit manually when the packet has been unloaded
from the receive FIFO.
July 03, 2014
949
Texas Instruments-Production Data