LM3S5G31 Datasheet, PDF (11/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S5G31 Microcontroller High-Level Block Diagram ............................... 42
Figure 2-1. CPU Block Diagram ............................................................................................. 65
Figure 2-2. TPIU Block Diagram ............................................................................................ 66
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 68
Figure 2-4. Bit-Band Mapping ................................................................................................ 89
Figure 2-5. Data Storage ....................................................................................................... 90
Figure 2-6. Vector Table ........................................................................................................ 96
Figure 2-7. Exception Stack Frame ........................................................................................ 98
Figure 3-1. SRD Use Example ............................................................................................. 112
Figure 4-1. JTAG Module Block Diagram .............................................................................. 173
Figure 4-2. Test Access Port State Machine ......................................................................... 176
Figure 4-3. IDCODE Register Format ................................................................................... 182
Figure 4-4. BYPASS Register Format ................................................................................... 183
Figure 4-5. Boundary Scan Register Format ......................................................................... 183
Figure 5-1. Basic RST Configuration .................................................................................... 187
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 187
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 188
Figure 5-4. Power Architecture ............................................................................................ 191
Figure 5-5. Main Clock Tree ................................................................................................ 194
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 287
Figure 6-2. Using a Crystal as the Hibernation Clock Source ................................................. 290
Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 290
Figure 7-1. Internal Memory Block Diagram .......................................................................... 313
Figure 8-1. μDMA Block Diagram ......................................................................................... 360
Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 366
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 368
Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 369
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 371
Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 372
Figure 9-1. Digital I/O Pads ................................................................................................. 424
Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 425
Figure 9-3. GPIODATA Write Example ................................................................................. 426
Figure 9-4. GPIODATA Read Example ................................................................................. 426
Figure 10-1. EPI Block Diagram ............................................................................................. 476
Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 484
Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 484
Figure 10-4. SDRAM Write Cycle ........................................................................................... 485
Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 491
Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 493
Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 494
Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 494
Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual
CSn .................................................................................................................. 495
Figure 10-10. Continuous Read Mode Accesses ...................................................................... 495
July 03, 2014
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Texas Instruments-Production Data