LM3S5G31 Datasheet, PDF (15/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Stellaris^® LM3S5G31 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Revision History .................................................................................................. 34
Documentation Conventions ................................................................................ 39
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 68
Processor Register Map ....................................................................................... 69
PSR Register Combinations ................................................................................. 74
Memory Map ....................................................................................................... 82
Memory Access Behavior ..................................................................................... 85
SRAM Memory Bit-Banding Regions .................................................................... 87
Peripheral Memory Bit-Banding Regions ............................................................... 87
Exception Types .................................................................................................. 93
Interrupts ............................................................................................................ 94
Exception Return Behavior ................................................................................... 99
Faults ................................................................................................................. 99
Fault Status and Fault Address Registers ............................................................ 101
Cortex-M3 Instruction Summary ......................................................................... 103
Core Peripheral Register Regions ....................................................................... 106
Memory Attributes Summary .............................................................................. 109
TEX, S, C, and B Bit Field Encoding ................................................................... 112
Cache Policy for Memory Attribute Encoding ....................................................... 113
AP Bit Field Encoding ........................................................................................ 113
Memory Region Attributes for Stellaris Microcontrollers ........................................ 113
Peripherals Register Map ................................................................................... 114
Interrupt Priority Levels ...................................................................................... 141
Example SIZE Field Values ................................................................................ 169
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 173
JTAG_SWD_SWO Signals (108BGA) ................................................................. 174
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 175
JTAG Instruction Register Commands ................................................................. 180
System Control & Clocks Signals (100LQFP) ...................................................... 184
System Control & Clocks Signals (108BGA) ........................................................ 184
Reset Sources ................................................................................................... 185
Clock Source Options ........................................................................................ 192
Possible System Clock Frequencies Using the SYSDIV Field ............................... 195
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 195
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 196
System Control Register Map ............................................................................. 201
RCC2 Fields that Override RCC Fields ............................................................... 222
Hibernate Signals (100LQFP) ............................................................................. 287
Hibernate Signals (108BGA) .............................................................................. 288
Hibernation Module Clock Operation ................................................................... 294
Hibernation Module Register Map ....................................................................... 296
Flash Memory Protection Policy Combinations .................................................... 317
User-Programmable Flash Memory Resident Registers ....................................... 321
Flash Register Map ............................................................................................ 321
μDMA Channel Assignments .............................................................................. 361
Request Type Support ....................................................................................... 363
July 03, 2014
15
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