LM3S5G31 Datasheet, PDF (528/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

External Peripheral Interface (EPI)
Bit/Field
7:6
5:0
Name
WRWS
reserved
Type
R/W
RO
Reset
0x0
Description
CS1n Write Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state encoding adds 2 EPI clock cycles to the access time.
Value Description
0x0 Active WRn is 2 EPI clocks
0x1 Active WRn is 4 EPI clocks.
0x2 Active WRn is 6 EPI clocks
0x3 Active WRn is 8 EPI clocks
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
528
July 03, 2014
Texas Instruments-Production Data