C8051F352 Datasheet, PDF (99/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
11. Memory Organization and SFRs
The memory organization of the C8051F350/1/2/3 is similar to that of a standard 8051. There are two sep-
arate memory spaces: program memory and data memory. Program and data memory share the same
address space but are accessed via different instruction types. The memory map is shown in Figure 11.1.
PROGRAM/DATA MEMORY
(Flash)
0x1FFF
0x1E00
0x1DFF
RESERVED
0xFF
0x80
0x7F
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
0xFFFF
EXTERNAL DATA ADDRESS SPACE
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
Figure 11.1. Memory Map
11.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F350/1/2/3 implements 8 kB of this pro-
gram memory space as in-system, re-programmable Flash memory, organized in a contiguous block from
addresses 0x0000 to 0x1DFF. Addresses above 0x1DFF are reserved.
Program memory is normally assumed to be read-only. However, the C8051F350/1/2/3 can write to pro-
gram memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX write instruc-
tion. This feature provides a mechanism for updates to program code and use of the program memory
space for non-volatile data storage. Refer to Section “15. Flash Memory’ on page 121 for further details.
Rev. 1.1
99