C8051F352 Datasheet, PDF (223/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 23.2. PCA0MD: PCA Mode
R/W
R/W
R/W
R
CIDL WDTE WDLCK
—
Bit7
Bit6
Bit5
Bit4
R/W
CPS2
Bit3
R/W
CPS1
Bit2
R/W
CPS0
Bit1
R/W
Reset Value
ECF 01000000
Bit0
Bit
Addressable
SFR Address: 0xD9
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–1:
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
UNUSED. Read = 0b, Write = don't care.
CPS2–CPS0: PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter.
CPS2
0
0
CPS1
0
0
CPS0
Timebase
0 System clock divided by 12
1 System clock divided by 4
0
1
0 Timer 0 overflow
0
1
1
High-to-low transitions on ECI (max rate = system clock
divided by 4)
1
0
0 System clock
1
0
1 External clock divided by 8*
1
1
0 Reserved
1
1
1 Reserved
*Note: External oscillator source divided by 8 is synchronized with the system clock.
Bit0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
Rev. 1.1
223