C8051F352 Datasheet, PDF (45/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
The offset calibration value adjusts the zero point of the ADC’s transfer function. It is stored as a two’s
complement, 24-bit number. An offset calibration which results in a full-scale positive (0x7FFFFF) or full-
scale negative (0x800000) result will cause an ADC error condition.
The Offset Calibration results are stored in registers ADC0COH, ADC0COM, and ADC0COL. The weight-
ing of the bits in the offset register (in LSBs) are shown below:
24-bit ADC (C8051F350/1)
ADC0COH
ADC0COM
ADC0COL
MSB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
–2²³ 2²² 2²¹ 2²⁰ 2¹⁹ 2¹⁸ 2¹⁷ 2¹⁶ 2¹⁵ 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹ 2⁸ 2⁷ 2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰
16-bit ADC (C8051F352/3)
ADC0COH
ADC0COM
ADC0COL
MSB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
–2¹⁵ 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹ 2⁸ 2⁷ 2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰ 2^–1 2^–2 2^–3 2^–4 2^–5 2^–6 2^–7 2^–8
Figure 5.3. ADC0 Offset Calibration Register Coding
The gain calibration value adjusts the slope of the ADC’s transfer function. The gain calibration regsiter
can range from 0 to 2 – 2^–23. A gain calibration which results in either of these extremes will cause an
ADC error condition.
The Gain Calibration results are stored in registers ADC0CGH, ADC0CGM, and ADC0CGL, as follows:
ADC0CGH
ADC0CGM
ADC0CGL
MSB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
2⁰ 2^–1 2^–2 2^–3 2^–4 2^–5 2^–6 2^–7 2^–8 2^–9 2^–10 2^–11 2^–12 2^–13 2^–14 2^–15 2^–16 2^–17 2^–18 2^–19 2^–20 2^–21 2^–22 2^–23
Example Decoding for Gain Register setting of 0x940000 (10010100 00000000 00000000b):
Slope Adjustment = 2⁰ + 2^–3 + 2^–5 = 1.0 + 0.125 + 0.03125 = 1.15625
Figure 5.4. ADC0 Gain Calibration Register Coding
Rev. 1.1
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