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C8051F352 Datasheet, PDF (83/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family | |||
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C8051F350/1/2/3
9.1. Comparator0 Inputs and Outputs
Figure 9.3 shows the external pin connections for the comparator. The positive and negative inputs to the
comparator can each be routed to one of eight different pins using the comparator mux. Comparator out-
puts can optionally be routed to port pins using the Crossbar circuitry.
The comparator inputs (CP0+ and CP0â) are selected in the CPT0MX register (SFR Definition 9.3). The
CMX0P1âCMX0P0 bits select the comparatorâs positive input; the CMX0N1âCMX0N0 bits select the com-
paratorâs negative input. Important Note About Comparator Inputs: The Port pins selected as compara-
tor inputs should be configured as analog inputs in their associated Port configuration register, and
configured to be skipped by the Crossbar.
Two versions of the comparator output can be routed to port pins, using the Port I/O Crossbar. The raw
(asynchronous) comparator output CP0A is enabled using bit 5 in the XBR0 register, and will be available
at P1.4. The CP0 output (synchronized to SYSCLK) is available at P1.5 when it is enabled with bit 4 in the
XBR0 register.
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
XBR0
VDD
CP0 +
+
CP0 -
-
GND
SET
DQ
Q
CLR
SET
DQ
Q
CLR
(SYNCHRONIZER)
0
P1.5
1
CP0
0
P1.4
1
CP0A
CPT0MX
Figure 9.3. Comparator Pin Connections
Rev. 1.1
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