C8051F352 Datasheet, PDF (179/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Table 20.3. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
Frequency: 22.1184 MHz
Baud Rate Oscilla- Timer Clock SCA1–SCA0 T1M* Timer 1
% Error tor Divide Source
(pre-scale
Reload
Factor
select)*
Value (hex)
0.00%
96
SYSCLK
XX
1
0xD0
0.00%
192
SYSCLK
XX
1
0xA0
0.00%
384
SYSCLK
XX
1
0x40
0.00%
768 SYSCLK / 12
00
0
0xE0
0.00%
1536 SYSCLK / 12
00
0
0xC0
0.00%
2304 SYSCLK / 12
00
0
0xA0
0.00%
9216 SYSCLK / 48
10
0
0xA0
0.00%
18432 SYSCLK / 48
10
0
0x40
0.00%
96
EXTCLK / 8
11
0
0xFA
0.00%
192
EXTCLK / 8
11
0
0xF4
0.00%
384
EXTCLK / 8
11
0
0xE8
0.00%
768
EXTCLK / 8
11
0
0xD0
0.00%
1536 EXTCLK / 8
11
0
0xA0
0.00%
2304 EXTCLK / 8
11
0
0x70
X = Don’t care
*Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1.
Table 20.4. Timer Settings for Standard Baud Rates
Using an External 18.432 MHz Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
Frequency: 18.432 MHz
Baud Rate Oscilla- Timer Clock SCA1–SCA0 T1M* Timer 1
% Error tor Divide Source
(pre-scale
Reload
Factor
select)*
Value (hex)
0.00%
80
SYSCLK
XX
1
0xD8
0.00%
160
SYSCLK
XX
1
0xB0
0.00%
320
SYSCLK
XX
1
0x60
0.00%
640 SYSCLK / 4
01
0
0xB0
0.00%
1280 SYSCLK / 4
01
0
0x60
0.00%
1920 SYSCLK / 12
00
0
0xB0
0.00%
7680 SYSCLK / 48
10
0
0xB0
0.00%
15360 SYSCLK / 48
10
0
0x60
0.00%
80
EXTCLK / 8
11
0
0xFB
0.00%
160 EXTCLK / 8
11
0
0xF6
0.00%
320
EXTCLK / 8
11
0
0xEC
0.00%
640 EXTCLK / 8
11
0
0xD8
0.00%
1280 EXTCLK / 8
11
0
0xB0
0.00%
1920 EXTCLK / 8
11
0
0x88
X = Don’t care
*Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1.
Rev. 1.1
179