C8051F352 Datasheet, PDF (64/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Table 5.7. ADC0 Fast Filter Typical RMS Noise (µV)
Decimation Output Word
PGA Gain Setting
Ratio
Rate*
1
2
4
8
16
32
1920
10 Hz
4.84 2.68 1.55 1.03 0.75
768
25 Hz
17.92 9.77 5.85 3.72 2.79
640
30 Hz
29.98 14.84 7.81 5.39 3.89
384
50 Hz
103.93 48.53 25.71 14.07 9.24
320
60 Hz
171.12 89.87 42.99 23.05 13.81
192
100 Hz 550.29 305.55 140.58 72.90 40.97
*Note: Output Word Rate assuming Modulator Clock frequency = 2.4576 MHz
(sampling clock frequency = 19.2 kHz)
0.61
2.45
3.27
7.17
10.33
25.52
64
0.56
2.28
3.19
6.45
9.00
19.96
128
0.58
2.21
3.03
6.06
8.52
17.68
Table 5.8. ADC0 Fast Filter Effective Resolution¹ in Unipolar Mode (bits)
Decimation ^{Output Word}
PGA Gain Setting
Ratio
Rate²
1
2
4
8
16
32
64
128
1920
10 Hz
18.98 18.83 18.62 18.21 17.67 16.97 16.09 15.04
768
25 Hz
17.09 16.97 16.71 16.36 15.77 14.96 14.06 13.11
640
30 Hz
16.35 16.36 16.29 15.82 15.29 14.54 13.58 12.65
384
50 Hz
14.55 14.65 14.57 14.44 14.05 13.41 12.56 11.65
320
60 Hz
13.83 13.76 13.83 13.73 13.47 12.88 12.08 11.16
192
100 Hz
12.15 12.00 12.12 12.07 11.90 11.58 10.93 10.11
Notes:
1. Effective
Resolution
=
log₂
⎛
⎝
F_-----u_--R-l_--l_-M-I_--n_--S--p_---u_-N--t_--oR---i-a_-s---ne_---(g_---Ve----()_--V_----)_⎠⎞
where Full Input Range = --------^V----^R---^E---^F--------- in Unipolar mode and RMS Noise is obtained from Table 5.7.
PGA Gain
2. Output Word Rate assuming Modular Clock frequency = 2.4576 MHz (sampling clock frequency = 19.2 kHz)
64
Rev. 1.1