C8051F352 Datasheet, PDF (120/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Table 14.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
/RST Output Low Voltage
/RST Input High Voltage
I_OL = 8.5 mA, V_DD = 2.7 to 3.6 V
—
0.7 x V_DD
/RST Input Low Voltage
—
/RST Input Pullup Current
/RST = 0.0 V
—
V_DD Monitor Threshold (V_RST)
Missing Clock Detector Timeout
Time from last system clock rising
edge to reset initiation
2.40
100
Reset Time Delay
Delay between release of any reset
source and code execution at loca- 5.0
tion 0x0000
Minimum /RST Low Time to
Generate a System Reset
15
V_DD Monitor Turn-on Time
100
V_DD Monitor Supply Current
—
V_DD Ramp Time
V_DD = 0 V to V_RST
—
Typ
—
—
—
25
2.55
220
—
—
—
20
—
Max Units
0.6
V
—
V
0.3 x V_DD
40
µA
2.70
V
600
µs
—
µs
—
µs
—
µs
50
µA
1
ms
120
Rev. 1.1