C8051F352 Datasheet, PDF (193/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Table 21.1. SPI Slave Timing Parameters
Parameter
Description
Min
Master Mode Timing* (See Figure 21.6 and Figure 21.7)
T_MCKH
SCK High Time
1 x T_SYSCLK
T_MCKL
SCK Low Time
T_MIS
MISO Valid to SCK Sample Edge
T_MIH
SCK Sample Edge to MISO Change
Slave Mode Timing* (See Figure 21.8 and Figure 21.9)
1 x T_SYSCLK
20
0
T_SE
T_SD
T_SEZ
T_SDZ
T_CKH
T_CKL
T_SIS
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
2 x T_SYSCLK
2 x T_SYSCLK
—
—
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
T_SIH
T_SOH
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
2 x T_SYSCLK
—
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK) in ns.
Max
Units
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
Rev. 1.1
193