C8051F352 Datasheet, PDF(117/234 Page) Silicon Laboratories – 8 k ISP Flash MCU Family

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

C8051F352 Datasheet, PDF (117/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

◁

C8051F350/1/2/3

14.2. Power-Fail Reset / VDD Monitor

When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply

monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 14.2). When VDD

returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though inter-

nal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD

dropped below the level required for data retention. If the PORSF flag reads â1â, the data may no longer be

valid. The VDD monitor is enabled and selected as a reset source after power-on resets; however its

defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor

is disabled by software, and a software reset is performed, the VDD monitor will still be disabled after the

reset. To protect the integrity of Flash contents, it is strongly recommended that the VDD monitor

remain enabled and selected as a reset source if software contains routines which erase or write

Flash memory.

The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor as a

reset source before it is enabled and stabilized may cause a system reset. The procedure for re-enabling

the VDD monitor and configuring the VDD monitor as a reset source is shown below:

Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = â1â).

Step 2. Wait for the VDD monitor to stabilize (see Table 14.1 for the VDD Monitor turn-on time).

Note: This delay should be omitted if software contains routines which erase or

write Flash memory.

Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = â1â).

See Figure 14.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.

See Table 14.1 for complete electrical characteristics of the VDD monitor.

SFR Definition 14.1. VDM0CN: VDD Monitor Control

R/W

VDMEN

Bit7

R

R

R

R

R

R

R

Reset Value

VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xFF

Bit7:

Bit6:

Bits5â0:

VDMEN: VDD Monitor Enable.

This bit is turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system

resets until it is also selected as a reset source in register RSTSRC (SFR Definition 14.2).

The VDD Monitor must be allowed to stabilize before it is selected as a reset source. Select-

ing the VDD monitor as a reset source before it has stabilized may generate a system

reset. See Table 14.1 for the minimum VDD Monitor turn-on time.

0: VDD Monitor Disabled.

1: VDD Monitor Enabled (default).

VDD STAT: VDD Status.

This bit indicates the current power supply status (VDD Monitor output).

0: VDD is at or below the VDD monitor threshold.

1: VDD is above the VDD monitor threshold.

Reserved. Read = Variable. Write = donât care.

Rev. 1.1

117

▷