C8051F352 Datasheet, PDF (127/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
16. External RAM
The C8051F350/1/2/3 devices include 512 bytes of RAM mapped into the external data memory space. All
of these address locations may be accessed using the external move instruction (MOVX) and the data
pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit
address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Mem-
ory Interface Control Register (EMI0CN as shown in SFR Definition 16.1). Note: the MOVX instruction is
also used for writes to the Flash memory. See Section “15. Flash Memory’ on page 121 for details. The
MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 7-bits of the 16-bit external data memory address word
are "don't cares". As a result, the 512-byte RAM is mapped modulo style over the entire 64 k external data
memory address range. For example, the XRAM byte at address 0x0000 is shadowed at addresses
0x0200, 0x0400, 0x0600, 0x0800, etc. This is a useful feature when performing a linear memory fill, as the
address pointer doesn't have to be reset when reaching the RAM block boundary.
SFR Definition 16.1. EMI0CN: External Memory Interface Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
—
—
—
—
—
PGSEL 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xAA
Bits 7–1: UNUSED. Read = 0000000b. Write = don’t care.
Bit 0: PGSEL: XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory address
when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since
the upper (unused) bits of the register are always zero, the PGSEL determines which page
of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
Rev. 1.1
127