C8051F352 Datasheet, PDF (87/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
10. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The C8051F35x family has a superset of all the peripherals included with a standard 8051. See Sec-
tion “1. System Overview’ on page 17 for more information about the available peripherals. The CIP-51
includes on-chip debug hardware which interfaces directly with the analog and digital subsystems, provid-
ing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51 core includes the following features:
- Fully Compatible with MCS-51 Instruction
Set
- 50 MIPS Peak Throughput
- 256 Bytes of Internal RAM
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- Integrated Debug Logic
DATA BUS
ACCUMULATOR
TMP1
TMP2
PSW
ALU
B REGISTER
STACK POINTER
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
DATA BUS
BUFFER
D8
DATA POINTER
D8
PC INCREMENTER
SFR_ADDRESS
SFR
SFR_CONTROL
D8
BUS
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
RESET
CLOCK
CONTROL
LOGIC
PIPELINE
STOP
IDLE
POWER CONTROL
REGISTER
D8
D8
MEM_ADDRESS
MEM_CONTROL
MEMORY
A16
INTERFACE ^{MEM_WRITE_DATA}
MEM_READ_DATA
D8
INTERRUPT
INTERFACE
D8
SYSTEM_IRQs
EMULATION_IRQ
Figure 10.1. CIP-51 Block Diagram
Rev. 1.1
87