C8051F352 Datasheet, PDF (31/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
4. Pinout and Package Definitions
Name
V_DD
DGND
AV+
AGND
/RST
C2CK
P2.0/
C2D
P0.0
P0.1
P0.2/
XTAL1
P0.3/
XTAL2
P0.4
P0.5
Table 4.1. Pin Definitions for the C8051F350/1/2/3
Pin Numbers
‘F350 ‘F351
‘F352 ‘F353
Type Description
21 17 Power Digital Supply Voltage. Must be tied to +2.7 V to +3.6 V
power.
22 18 Ground Digital Ground. Must be tied to Ground.
10
6 Power Analog Supply Voltage. Must be tied to +2.7 V to +3.6 V
power.
9
5 Ground Analog Ground. Must be tied to Ground.
12
8
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1kΩ pull-up to V_DD is
recommended. See Reset Sources Section.
D I/O _{Clock signal for the C2 Debug Interface.}
11
7
D I/O Port 2.0. See Port I/O Section for a complete description.
D I/O Bi-directional data signal for the C2 Debug Interface.
13
9 D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
14 10 D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
15 11 D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
A In This pin is the external oscillator return for a crystal or reso-
nator. See Oscillator Section.
16 12 D I/O Port 0.3. See Port I/O Section for a complete description.
A I/O or This pin is the excitation driver for an external crystal or res-
D In onator, or an external clock input for CMOS, capacitor, or
RC oscillator configurations. See Oscillator Section.
17 13 D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
18 14 D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
Rev. 1.1
31