C8051F352 Datasheet, PDF (27/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
1.8. Port Input/Output
C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit
port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be config-
ured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain
operation. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled to save
power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip
conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on
the port pins using the Crossbar control resgiters. This allows the user to select the exact mix of general-
purpose port I/O, digital, and analog resources needed for the application.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
Highest
Priority
Lowest
Priority
2
UART
CP0
2
Outputs
4
SPI
2
SMBus
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
P2
Digital
Crossbar
8
P0
I/O
Cells
8
P1
I/O
Cells
P2
(P2.0)
I/O
Cell
P0.0
P0.7
P1.0
P1.7
P2.0
Figure 1.10. Port I/O Functional Block Diagram
Rev. 1.1
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