C8051F352 Datasheet, PDF (23/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
1.3. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 8 kB bytes of Flash. This memory may be reprogrammed in-system in 512
byte sectors, and requires no special off-chip programming voltage.
PROGRAM/DATA MEMORY
(Flash)
0x1FFF
0x1E00
0x1DFF
RESERVED
0xFF
0x80
0x7F
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
0xFFFF
EXTERNAL DATA ADDRESS SPACE
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
Figure 1.6. Memory Map
Rev. 1.1
23