C8051F352 Datasheet, PDF (49/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 5.2. ADC0CF: ADC0 Configuration
R
R
R
R/W
R
R/W
R
R
Reset Value
—
—
— AD0ISEL — AD0VREF —
— 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xFB
Bits 7–5: Unused: Read = 000b, Write = don’t care.
Bit 4: AD0ISEL: ADC0 Interrupt Source Select.
This bit selects which filter completion will set the AD0INT interrupt flag.
0: SINC3 filter.
1: FAST filter.
Bit 3: Unused: Read = 0b, Write = don’t care.
Bit 2: AD0VREF: ADC0 VREF Source Select.
0: ADC0 uses the internal VREF (2.5 V). Setting this bit to ‘0’ enables the internal Voltage
Reference.
1: ADC0 uses an external VREF.
Bits 1–0: Unused: Read = 00b, Write = don’t care.
This SFR can only be modified when ADC0 is in IDLE mode.
Rev. 1.1
49