C8051F352 Datasheet, PDF (167/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
19.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to
the SMBus specification.
Table 19.4. SMBus Status Decoding
Values Read
Current SMbus State
Typical Response Options
Values
Written
1110
0
0
X
A master START was generated.
Load slave address + R/W
into SMB0DAT.
00X
0
0
0
A master data or address byte
was transmitted; NACK received.
Set STA to restart transfer.
Abort transfer.
10X
01X
Load next data byte into
SMB0DAT.
00X
End transfer with STOP.
01X
1100
0
0
1
A master data or address byte
was transmitted; ACK received.
End transfer with STOP and
start another transfer.
1
1
X
Send repeated START.
10X
Switch to Master Receiver
Mode (clear SI without writ- 0 0 X
ing new data to SMB0DAT).
Rev. 1.1
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