C8051F352 Datasheet, PDF (52/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 5.6. ADC0DECL: ADC0 Decimation Ratio Register Low Byte
R/W
DECI7
Bit7
R/W
DECI6
Bit6
R/W
DECI5
Bit5
R/W
DECI4
Bit4
R/W
DECI3
Bit3
R/W
DECI2
Bit2
R/W
DECI1
Bit1
R/W
Reset Value
DECI0 11111111
Bit0
SFR Address: 0x9A
Bits 7–0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7–0.
This register contains the low byte of the 11-bit ADC Decimation Ratio. The decimation ratio
determines the number of modulator input samples used to generate a single output word
from the ADC.
The ADC0 decimation ratio is defined as:
Decimation Ratio = DECI[10:0] + 1
The corresponding sampling period and output word rate of ADC0 is:
ADC0 Conversion Period = [(DECI[10:0] + 1) * 128] / MDCLK
ADC0 Output Word Rate = MDCLK / [128 * (DECI[10:0] + 1)]
The minimum decimation ratio setting is 20. Any register setting below 19 will automatically
be interpreted as 19.
Important: When using the fast filter, the decimation ratio must be divisible by 8
(DECI[2:0] = 111b).
This SFR can only be modified when ADC0 is in IDLE mode.
SFR Definition 5.7. ADC0DAC: ADC0 Offset DAC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ADC0DAC
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xBF
Bits 7–0: ADC0DAC: ADC0 PGA Offset DAC Magnitude.
This register determines the ADC0 Offset DAC Magnitude. The value in the offset DAC is a
signed-magnitude representation. Bit 7 represents the sign value (0 = positive, 1 = nega-
tive), while Bits 6–0 represent the magnitude.
This SFR can only be modified when ADC0 is in IDLE mode.
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Rev. 1.1